1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to forming capacitors in the metallization system, such as capacitors for dynamic random access memories (DRAM), decoupling capacitors and the like.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation, to provide currently available integrated circuits with high performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance, while, however, increasing dynamic power consumption of the individual transistors. That is, due to the reduced switching time interval, the transient currents upon switching a MOS transistor element from logic low to logic high are significantly increased.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, are typically formed in integrated circuits that are used for a plurality of purposes, such as charge storage for storing information, for decoupling and the like. Decoupling in integrated circuits is an important aspect for reducing the switching noise of the fast switching transistors, since the decoupling capacitor may provide energy at a specific point of the circuitry, for instance at the vicinity of a fast switching transistor, and thus reduce voltage variations caused by the high transient currents which may otherwise unduly affect the logic state represented by the transistor.
Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC). Furthermore, in sophisticated micro-controller devices and other sophisticated devices, an increasing amount of storage capacity may be provided on chip with the CPU core, thereby also significantly enhancing the overall performance of modern computer devices. For example, in typical micro-controller designs, different types of storage devices may be incorporated so as to provide an acceptable compromise between die area consumption and information storage density versus operating speed. For example, static RAM memories may be formed on the basis of registers, thereby enabling an access time determined by the switching speed of the corresponding transistors in the registers. Typically, a plurality of transistors may be required to implement a corresponding static RAM cell, thereby significantly reducing the information storage density compared to, for instance, dynamic RAM (DRAM) memories including a storage capacitor in combination with a pass transistor. Thus, a higher information storage density may be achieved with DRAMs, although at a reduced access time compared to static RAMs, which may nevertheless render dynamic RAMs attractive for specific less time critical applications in complex semiconductor devices.
Frequently, the storage capacitors may be formed in the transistor level using a vertical or planar configuration. While the planar architecture may require significant silicon area for obtaining the required capacitance values, the vertical arrangement may necessitate complex patterning regimes for forming the deep trenches of the capacitors.
For these reasons, in other approaches, capacitors may also be implemented in the metallization system of the semiconductor device, i.e., in the metallization layers comprising metal lines and vias, wherein, however, typically, significant modifications of the overall process flow may be required to implement the metal capacitors in the metallization system and to provide the corresponding interconnect structure for connecting the metal capacitors with the circuit elements in the device level, such as transistors and the like. Consequently, also in this case, additional process modules may have to be implemented into the overall process flow, which may thus contribute to additional process complexity.
In other strategies, the storage capacitors of complex semiconductor devices, which require DRAM arrays in combination with logic circuit portions, an adapted process flow is applied in which the metallization system of the device may be formed for the memory area and the logic portion in a common process sequence, while on the other hand the contact level is used for incorporating the capacitors, which, however, may result in performance loss in the logic circuit portions, as will be described in more detail with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 in a manufacturing stage after incorporating a plurality of storage elements 130 and upon forming a metallization system 180 on the basis of a common process sequence for memory areas and other device areas in which logic circuit portions are to be provided. As shown, the device 100 comprises a substrate 101 which represents any appropriate carrier material for forming thereon a semiconductor layer 102, typically a silicon-based semiconductor layer, which comprises a plurality of semiconductor regions or active regions which are generally to be understood as semiconductor regions in which one or more transistor elements are to be formed. For example, semiconductor regions 102A, which are laterally delineated by respective isolation regions 102C, such as shallow trench isolations and the like, may be provided and may correspond to a plurality of transistors 150A, which may act as switches of a memory array for controlling the charging and discharging of the capacitors 130. On the other hand, an active region 102B is illustrated which represents the active region of one or more transistors 150B, which are to be considered as a part of a logic circuit portion, thereby requiring reduced overall signal propagation delay in this circuit portion. For example, the transistor 150B may comprise a gate electrode structure 160B having any appropriate configuration so as to comply with the overall requirements of performance driven transistor devices. It should be appreciated that in complex semiconductor devices the critical dimensions of circuit components, such as transistors and the like, have reached the deep sub-micron range, wherein overall device performance is significantly affected by the series resistance, the parasitic capacitance and generally the electric performance of any components external to the transistor 150B, such as the performance of a contact level 120 and a metallization system 180. On the other hand, for the transistors 150A, a high packing density is highly desirable in order to increase the overall information density in memory areas of the device 100, while at the same time a certain required capacitance of the capacitors 130 has to be implemented, however, without unduly increasing the lateral size of the capacitors 130 in order to not unduly affect the desired packing density.
Thus, the gate electrode structure 160B may be formed in accordance with required design rules, while corresponding “gate electrode structures” 160A, which also act as word lines of the plurality of transistors 150A when representing a memory array, are provided so as to have a similar configuration in terms of material composition and the like. Furthermore, in view of reducing the overall series resistance, the transistors 150A, 150B include contact regions 151A, 151B, respectively, for instance in the form of a metal silicide which exhibits higher conductivity compared to even highly doped semiconductor materials.
The contact level 120, which is generally to be understood as an “interface” between the semiconductor-based circuit elements 150A, 150B and the metallization system 180, is provided in the form of a first sublevel 120A in which one or more dielectric materials, indicated as material system 123A, are provided so as to enclose and passivate the circuit elements 150A, 150B. Moreover, contact elements 121A and 122A are provided in the dielectric material 123A so as to connect to the contact regions 151A, 151B as required in accordance with the overall circuit layout. Typically, the contact elements 121A, 122A include an appropriate contact metal, such as tungsten, possibly in combination with appropriate barrier materials, such as titanium, titanium nitride and the like. For convenience, any such barrier materials are not shown in FIG. 1. Furthermore, the contact level 120 comprises a second contact sublevel 120B comprising an appropriate dielectric material or materials, indicated as 123B. For example, the capacitors 130 are embedded in the dielectric material 123B and may have an appropriate configuration, for instance comprising a first electrode material 131 that is in contact with the respective contact elements 121A, followed by a dielectric material 132 which acts as the capacitor dielectric and which may be provided in the form of any appropriate dielectric material, such as conventional dielectric materials, high-k dielectric materials and the like. It should be appreciated that a high-k dielectric material is generally to be understood as a dielectric material having a dielectric constant of 10.0 and higher. Furthermore, a second electrode material 133 is provided in the capacitors 130 and is separated from the first electrode material 131 by the dielectric layer 132. Furthermore, a common electrode contact region or electrode “plate” 126A is formed above the capacitors 130, thereby connecting the electrode materials 133 of the various capacitors 130 so as to form a common electrode for a plurality of the capacitors 130. Furthermore, a contact element 125A is formed so as to connect to the common electrode 126A on the one side, and to the metallization system 180 on the other side.
Furthermore, the contact sublevel 120B comprises contact elements 125B formed so as to connect to the respective contact elements 122A and to connect to the metallization system 180. It should be appreciated that the metallization system 180 typically comprises a plurality of metallization layers, wherein, for convenience, the very first metallization layer 170 is illustrated in FIG. 1. The metallization layer 170 typically comprises a dielectric material 171 in combination with an etch stop material 172, wherein, in sophisticated applications, the dielectric material 171 may comprise a low-k dielectric material, i.e., a dielectric material having a dielectric constant of 3.0 and less, in order to reduce the parasitic capacitance in the metallization layer 170. On the other hand, the dielectric material 171 may provide superior etch stop capabilities, mechanical integrity and, if required, superior confinement of highly conductive metals such as copper and the like. For example, metal lines or generally metal regions 173 formed in the metallization layer 170 may comprise a metal of superior conductivity, wherein, as indicated before, in sophisticated applications, a highly conductive material such as copper is used, while in other cases aluminum and the like is frequently implemented, depending on the overall device requirements. Consequently, the contact elements 125B have a height that is substantially determined by the requirements to be applied for forming the capacitors 130, wherein, in sophisticated applications, a thickness of the sublevel 120B may be several hundred nanometers, which may significantly contribute to the overall series resistance, in particular when the contact level 120 is formed on the basis of well-established contact materials, such as tungsten, which may exhibit a significantly lower conductivity compared to highly conductive metals, such as copper.
The semiconductor device 100 as shown in FIG. 1 may be formed on the basis of the following process strategy. First, the semiconductor regions or active regions 102A, 102B are formed by incorporating the isolation regions 102C and incorporating an appropriate dopant profile in the various regions so as to comply with the required transistor characteristics for the devices 150A, 150B. Thereafter, the gate electrode structures 160B, 160A, i.e., the word lines, may be formed on the basis of well-established process strategies, for instance, comprising the deposition or formation of appropriate gate dielectric materials followed by the deposition of gate electrode materials, such as polysilicon and the like, and a patterning process based on sophisticated lithography techniques and anisotropic etch strategies. If required, at least some process steps may be applied differently for the gate electrode structures 160B on the one side and for the gate electrode structures or generally word lines 160A on the other side. Thereafter, drain and source regions may be formed by ion implantation, epitaxial growth techniques and the like, followed by any anneal processes, thereby completing the basic transistor configuration. Thereafter, the contact regions 151A, 151B are formed on the basis of well-established silicidation techniques, followed by the deposition of the dielectric material or materials 123A. Based on well-established contact techniques, the contact elements 121A, 122A may be formed in a common process sequence for the devices 150A, 150B, while additionally any “buried” contact elements 124A are provided so as to appropriately connect to the transistors 150A (shown in dashed lines), thereby forming bit lines for the memory array formed by the transistors 150A in combination with the word lines or gate electrode structures 160A. Thereafter, a portion of the material 123B may be patterned so as to obtain corresponding openings for the capacitors 130 and possibly for a portion of the contact elements 125B, depending on the overall process strategy. Thereafter, the electrode material 131 may be deposited and recessed by using well-established deposition and patterning processed, followed by the deposition of the dielectric layer 132 and the filling in of the electrode material 133. Next, the contact plate 126A may be provided, for instance as an excess portion of the material 133, depending on the process strategy to be applied, followed by forming the contact element 125A. At least during some of the process steps applied to form the capacitors 130, the contact openings 125B may also be formed, while in other cases a separate process sequence may be applied for forming the contact elements 125B. Consequently, after completing the sublevel 120B, the further processing may be continued commonly for the non-memory devices 150B and the transistors 150A by forming the metallization layer 170. To this end, the materials 172, 171 may be deposited and may be patterned so as to receive appropriate openings, which are then refilled by a desired conductive material, possibly in combination with a barrier material (not shown) when, for instance, copper-based metals are used for the metal regions 173. Thereafter, excess material may be removed and the further processing may be continued by forming a further metallization layer of the system 180, for instance by depositing a corresponding etch stop layer, such as the layer 172.
Consequently, although the conventional process strategy described with reference to the device 100 may allow the fabrication of the metallization system 180, commonly for non-memory areas and memory areas of the device 100, thereby significantly enhancing overall process efficiency compared to process strategies in which different process strategies have to be applied for forming capacitors in the metallization system 180, the resulting device configuration above the performance-driven circuit elements 150B may result in increased signal propagation delay caused by the contact elements 125B.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.